Portrait of Yuntao Lu

Yuntao Lu

鲁云涛 in Chinese
Ph.D. Student
Department of Computer Science and Engineering
The Chinese University of Hong Kong

Biography

I am a Ph.D. student in Computer Science at the Chinese University of Hong Kong (CUHK), under the supervision of Prof. Bei Yu. I hold an M.S. degree in Information Studies from the University of Texas at Austin (UT Austin) in 2020 and an M.S. degree in Computer Science from the University of Science and Technology of China (USTC), under the supervision of Prof. Xuehai Zhou and Prof. Chao Wang, in 2018. I obtained a B.Eng. degree in Software Engineering from the University of Electronic Science and Technology of China (UESTC) in 2015.

Research Interests

Publications

Conference Papers

  1. Jiaxi Jiang, Yuxuan Zhao, Zhen Zhuang, Siting Liu, Yuntao Lu, Yuhao Ji, Yifan Shi, Xuanqi Chen, Tsung-Yi Ho, Yibo Lin, and Bei Yu, “MoL-PAM: Joint PG TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic,” accepted by IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, Jan. 25–28, 2027.
  2. Peiyi Han, Yuntao Lu, Haiyang Liu, Fangzhou Liu, Xufeng Yao, and Yuyang Ye, “LLM4SDC: Leveraging Multi-Agent System for Automated SDC Generation and Benchmarking,” ACM/IEEE The Chips to Systems Conference (DAC), San Francisco, USA, Jul. 12–16, 2026.
  3. Mingjun Wang, Yihan Wen, Yuntao Lu, Mingjun Wang, Xufeng Yao, and Bei Yu, “MoL-PAM: Joint PG TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic,” International Conference on Learning Representations (ICLR), Rio de Janeiro, Brazil, Apr. 23–27, 2026.
  4. Hongduo Liu, Yuntao Lu, Fengrui Liu, Yuxiang Zhao, Boyu Han, Jianan Mu, Yibo Lin, Runsheng Wang, Huawei Li, and Bei Yu, “LLM-Assisted Circuit Verification: A Comprehensive Survey,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Hong Kong, China, Jan. 19–22, 2026, pp. 439–446.
  5. Yuntao Lu, Mingjun Wang, Yihan Wen, Boyu Han, Jianan Mu, Huawei Li, and Bei Yu, “VIRTUAL: Vector-based Dynamic Power Estimation via Decoupled Multi-Modality Learning,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Oct. 26–30, 2025.
  6. Yuhao Ji, Yuntao Lu, Zuodong Zhang, Zizheng Guo, Yibo Lin, and Bei Yu, “DiffCCD: Differentiable Concurrent Clock and Data Optimization,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Oct. 26–30, 2025.
  7. Yuntao Lu, Dehua Liang, Siting Liu, Yuhao Ji, Yu Zhang, Xuanqi Chen, Xia Lin, Jinlei Lu, Weihua Sheng, and Bei Yu, “A Hybrid Optimization Framework for Power-Efficient Pulsed Latch Utilization in Clock Networks,” ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD), Santa Cruz, USA, Sep. 8–10, 2025.
  8. Yuntao Lu, Lei Gong, Chongchong Xu, Fan Sun, Yiwei Zhang, Chao Wang, and Xuehai Zhou, “A High-performance FPGA Accelerator for Sparse Neural Networks: Work-in-Progress,” International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion (CASES), Seoul, Korea, Oct. 15–20, 2017.
  9. Chongchong Xu, Jinhong Zhou, Yuntao Lu, Fan Sun, Lei Gong, Chao Wang, Xi Li, and Xuehai Zhou, “Evaluation and Trade-offs of Graph Processing for Cloud Services,” IEEE International Conference on Web Services (ICWS), Honolulu, USA, Jun. 25–30, 2017.

Journal Papers

  1. Yuhao Ji, Jiaxi Jiang, Siting Liu, Yifan Shi, Yuntao Lu, Peng Xu, Xinyun Zhang, Ziyi Wang, Yibo Lin, and Bei Yu, “LibTimer: Addressing Library Evolution in Pre-Routing Timing Prediction via Continuous Library Representation,” accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.
  2. Yuntao Lu, Chen Bai, Yuxuan Zhao, Ziyue Zheng, Yangdi Lyu, Mingyu Liu, and Bei Yu, “DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 31, no. 04, pp. 70:1–70:23, 2026.
  3. Yuntao Lu, Lei Gong, Chao Wang, and Xuehai Zhou, “SparseNN: A Performance-Efficient Accelerator for Large-Scale Sparse Neural Networks,” International Journal of Parallel Programming (IJPP), vol. 46, no. 4, pp. 789–805, 2018.

Book Chapters

  1. Yuntao Lu, Chao Wang, Lei Gong, Xi Li, Aili Wang, and Xuehai Zhou, “Overview of Neural Network Accelerators,” In High Performance Computing for Big Data: Methodologies and Applications, Chapman and Hall/CRC, 2017, pp. 107–120.

Experience

Intel Asia-Pacific Research & Development Ltd

Machine Learning Engineer, Intel-Optimized TensorFlow Framework Validation TeamJan. 2022–Aug. 2023 · Shanghai, China

  • Maintained daily performance validation for AI models and monthly releases of Intel-Optimized TensorFlow by implementing testing automation workflows and performance monitoring tools.

Institute of Computing Technology, Chinese Academy of Sciences

AI Applied Engineer, Intelligent Processor Research CenterAug. 2020–Dec. 2021 · Beijing, China

  • Migrated and deployed optimized AI models and applications on neural processing units and customized devices.